Integrated circuit having a memory cell transistor with a gate oxide layer which is thicker than the gate oxide layer of a peripheral circuit transistor

US6066881A · kind A · utility

Assignee

• Mitsubishi Electric Corporation · JP

Inventors

• Masahiro Shimizu · Tokyo, JP
• Yoshinori Tanaka · Yokohama, JP
• Hideaki Arima · Kasai, JP

Key dates

• Filing date: Jul 20, 1998
• Grant date: May 23, 2000
• Expiry date: Jul 20, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/033

Abstract

A gate insulating film in a memory cell portion is thicker than a gate insulating film in a peripheral circuitry. Source/drain of an MOS transistor in the memory cell portion have double-diffusion-layer structures, respectively, and source/drain of an MOS transistor in the peripheral circuitry have triple-diffusion-layer structures, respectively.