LOC semiconductor package
US6066887A · kind A · utility
6Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1998 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Feb 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor package includes a semiconductor chip having a plurality of bonding pads on its top surface, a plurality of inner leads located above the semiconductor chip and electrically connected to the bonding pads by wire, a plurality of outer leads extending from the respective inner leads, and at least one bus bar formed lower than the inner leads, to prevent electrical shorts and improve reliability of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.