Full duplex buffer management and apparatus
US6067408A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 1996 |
| Grant date | May 23, 2000 |
| Priority date | — |
| Expiry date | Feb 22, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.