Method of manufacturing embedded DRAM

US6069037A · kind A · utility

Assignee

• United Silicon Incorporated · TW

Inventor

• Kuan-Yang Liao · Taipei, TW

Key dates

• Filing date: Nov 13, 1998
• Grant date: May 30, 2000
• Expiry date: Nov 13, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A method of manufacturing embedded DRAM whose DRAM gate is formed from a tungsten silicide layer and a polysilicon layer and whose logic gate is formed from a self-aligned silicide layer and a polysilicon layer. Moreover, the polysilicon layer in the DRAM gate and the logic gate has different thickness. The method of forming embedded DRAM includes the steps of forming a DRAM gate pattern and a logic gate pattern on a first photoresist layer. Next, the underlying silicon nitride layer, tungsten silicide layer and the second polysilicon layer are etched to form a DRAM gate structure. Thereafter, a second photoresist layer is formed over the DRAM circuit region. Finally, using the remaining silicon nitride layer, tungsten silicide layer and second polysilicon layer as an etching mask, the exposed layers in the logic circuit region are etched to form a logic gate composed of the first polysilicon layer, only. Consequently, only two photoresist masks are needed in the fabrication of DRAM gate and logic gate, and hence the degree of complexity in manufacture is greatly reduced.