Method of manufacturing a semiconductor integrated circuit device

US6069038A · kind A · utility

Assignee

• HITACHI, LTD. · JP

Inventors

• Takashi Hashimoto · Fukuoka, JP
• Kenichi Kuroda · Tokyo, JP
• Shoji Shukuri · Koganei, JP

Key dates

• Filing date: Sep 10, 1999
• Grant date: May 30, 2000
• Expiry date: Sep 10, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A silicon nitride film is left behind on only regions for forming the gate electrodes (word lines) of memory-cell selecting MISFETs constituting a DRAM, and it is not left behind on either of the gate electrodes of MISFETs constituting a logic LSI and those of MISFETs constituting the memory cells of an SRAM. Thereafter, the gate electrodes (word lines) in the DRAM and the gate electrodes in the logic LSI and the SRAM are simultaneously patterned by etching which employs the silicon nitride film and a photoresist film as a mask. Thus, in the manufacture of a semiconductor integrated circuit device wherein both the DRAM and the logic LSI are mounted, a contact hole forming process (gate-SAC) for the DRAM is made compatible with a contact hole forming process (L-SAC).