Ferroelectric memory transistor with resistively coupled floating gate
US6069381A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1997 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Sep 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention proposes a new type of single-transistor memory device, which stores information using the polarization of a ferroelectric material. The device is a floating-gate FET, with a ferroelectric material positioned between the gate and the floating gate, and a resistance, preferably in the form of a thin SiO.sub.2 dielectric between the floating gate and the transistor channel. Unlike previous designs, in this device the floating gate is both capacitively and resistively coupled to the transistor channel, which enables the device to be both read and written using low voltages. This device offers significant advantages for operation at low voltages and at high speeds, for repeated cycling of over 10.sup.10 times, since device durability is limited by the ferroelectric endurance rather than oxide breakdown, and for integration at gigabit densities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.