Programmable logic device circuitry for improving multiplier speed and/or efficiency
US6069487A · kind A · utility
96Cited by
3References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Jun 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17732
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In order to facilitate the performance of multiplications in programmable logic devices, individual logic modules of such devices are constructed so that one logic module can perform (at least) both one place of binary multiplication and one place of full binary addition. This makes it possible to reduce the number of logic modules that are required to perform a multiplication. It also reduces the number of inter-module connections employed in a multiplication, thereby tending to decrease the time required to perform a multiplication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.