High-speed logic embodied differential dynamic CMOS true single phase clock latches and flip-flops with single transistor clock latches
US6069495A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1997 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Nov 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1738
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A differential true single phase latch and flip-flop designed to embody logic functions is described. The logic function embodied latch includes a first circuit branch including first input switching devices for receiving a first set of input signals which include input signals and their corresponding complements and for outputting a first output signal having a logic state representative of the results of a logic function performed on said first set of input signals and a second circuit branch including second input switching devices for receiving the complement of the at least two input signals and can include the at least two input signals and for outputting a non-inverted output signal. First and second input switching devices are configured so as to cause the latch to perform logic functions on the input signals and latch output states corresponding to the results logic functions on its non-inverted and inverted outputs in the same clock phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.