Semiconductor memory device having storage nodes doped with first and second type impurities
US6069818A · kind A · utility
7Cited by
3References
6Claims
0Family size
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Key dates
| Filing date | Apr 29, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Apr 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/09
Abstract
A first impurity is implanted into source-drain regions of a first type of MOS transistor, a second impurity is implanted into source-drain regions of a second type of MOS transistor, and both first and second impurities are implanted into data storage nodes, whereby a double-layer structure is formed. The source-drain regions of the respective MOS transistors are further doped with another kind of impurity. Thus, a semiconductor memory device is provided which is free of depletion layer induced leak currents, the depletion layer being restrained to extend to the substrate surface by the impurity profile of the data storage nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.