Method for parallel programming of nonvolatile memory devices, in particular flash memories and EEPROMS
US6069822A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 1998 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Oct 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The programming method comprises the steps of applying a programming pulse to a first cell and simultaneously verifying the present threshold value of at least a second cell; then verifying the present threshold value of the first cell and simultaneously applying a programming pulse to the second cell. In practice, during the entire programming operation, the gate terminal of both the cells is biased to a same predetermined gate voltage and the source terminal is connected to ground; the step of applying a programming pulse is carried out by biasing the drain terminal of the cell to a predetermined programming voltage and the step of verifying is carried out by biasing the drain terminal of the cell to a read voltage different from the programming voltage. Thereby, switching between the step of applying a programming pulse and verifying is obtained simply by switching the drain voltage of the cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.