Method for multiple staged power up of integrated circuit
US6069832A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1997 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Aug 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A complementary metal-oxide semiconductor (CMOS) integrated circuit, such as a dynamic random access memory (DRAM), is powered by supply voltage. The CMOS integrated circuit is divided into n circuit portions including a first circuit portion and a second circuit portion. Control circuitry generates a first powerup control signal. A first switch couples the supply voltage to the first circuit portion based on the first powerup control signal being active. The first powerup control signal is delayed by a selected time delay to produce a second powerup control signal. Alternatively, the second powerup control signal is generated independent of the first powerup control signal, but is active the selected time delay after the first powerup control signal is active. A second switch couples the supply voltage to the second circuit portion based on the second powerup control signal being active.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.