Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
US6069839A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1999 |
| Grant date | May 30, 2000 |
| Priority date | — |
| Expiry date | Jan 27, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit including an address bus providing random addresses for a random access memory array, and a register configured to receive, store or transfer (i) a first random address from the address bus in response to a first periodic signal transition and (ii) a second random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle, and are preferably complementary to each other. In a further embodiment, the invention concerns a random access memory having an address bus providing random address information for a random access memory array, a predecoder configured to at least partially decode the random address information from the address bus, a register configured to receive, store or transfer (i) a first at least partially decoded random address from the address bus in response to a first periodic signal transition and (ii) a second at least partially decoded random address from the address bus in response to a second periodic signal transition, wherein the first and second periodic signal transitions occur within a single periodic signal cycle; and a postde…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.