Programmable I/O cell with dual boundary scan
US6071314A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318583
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided. Theses interconnect lines can be used to programmably connect the data output of a first cell to the data input of second cell which need not be adjacent to the first.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.