Method of making an efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection

US6071768A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Charvaka Duvvury · Plano, US
• David D. Briggs · Richardson, US
• Fernando D. Carvajal · McKinney, US

Key dates

• Filing date: May 8, 1997
• Grant date: Jun 6, 2000
• Expiry date: May 8, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/711

Abstract

A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.