Method for a self-aligned select gate for a split-gate flash memory structure
US6071777A · kind A · utility
10Cited by
4References
8Claims
0Family size
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Key dates
| Filing date | Apr 29, 1999 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Apr 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A process for making a self-aligned select gate for a split-gate flash memory structure uses a patterned nitride layer and a photoresist layer to serve as masks to define a select gate length, facilitates a self-aligned ion implantation to form a drain region of a memory cell, and defines a distance between the select gate and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.