Tunable threshold SOI device using isolated well structure for back gate
US6072217A · kind A · utility
154Cited by
4References
8Claims
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Key dates
| Filing date | Jun 11, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Jun 11, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
Abstract
To reduce threshold levels in fully depleted SOI devices having back gate wells, the channel regions of the devices are formed of an intrinsic or pseudo-intrinsic semiconductor. Also, multiple well structures or isolation regions are formed below the oxide layer to reduce diode junction leakage between the back gate wells of the devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.