Data-output driver circuit and method
US6072729A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 24, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Aug 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A drive circuit includes drive input and output terminals, a supply terminal, a drive transistor, and a drive-control circuit. The drive transistor includes a control terminal, a first transistor terminal coupled to the drive output terminal, and a second transistor terminal coupled to the supply terminal. The drive-control circuit has an input terminal coupled to the drive input terminal and has an output terminal coupled to the control terminal of the drive transistor. The drive-control circuit generates on the control terminal of the drive transistor a signal level that changes at a first rate during a first time period and at a second higher rate during a second time period following the first time period. As a result, when used as a data-output driver, one can adjust the first and second rates and time periods such that the drive circuit meets both the 50-ohm and 50 pf falling-slew-rate ranges specified in the Intel.RTM. PC-100 specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.