Memory device preventing a slow operation through a mask signal
US6072749A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Oct 5, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1018
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is a memory device with a structure that has eliminated the logic circuit using I/O mask signal DQM from within the critical path from the clock CLK to the predecoder and column decoder for generating column selection signal CL. The logic circuit using I/O mask signal DQM within the critical path for generating column selection signals is eliminated, and the time from when the clock is supplied until the column selection signal is generated is made as short as possible. On the other hand, to make an I/O mask possible during burst write mode, drive control of the write amplifier is performed based on I/O mask signal DQM. Specifically, activation of the write amplifier is prohibited or allowed in response to the I/O mask signal DQM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.