Data processing system having a data prefetch mechanism and method therefor
US6073215A · kind A · utility
122Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 3, 1998 |
| Grant date | Jun 6, 2000 |
| Priority date | — |
| Expiry date | Aug 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system (10) includes a mechanism for preventing DST line fetches from occupying the last available entries in a cache miss queue (50) of the data cache and MMU (16). This is done by setting a threshold value of available cache miss queue (50) buffers over which a DST access is not allowed. This prevents the cache miss queue (50) from filling up and preventing normal load and store accesses from using the cache miss queue (50).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.