Michael D. Snyder
50Patents
14h-index
66Co-inventors
87Inventor score
Filing activity: Sep 7, 1978 → Oct 11, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6073215A | Data processing system having a data prefetch mechanism and method therefor | Physics | 122 | Expired |
| US6202130A | Data processing system for processing vector data and method therefor | Physics | 111 | Expired |
| US6119203A | Mechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing system | Physics | 85 | Expired |
| US6269427A | Multiple load miss handling in a cache memory system | Physics | 60 | Expired |
| US5630095A | Method for use with a data coherency protocol allowing multiple snoop queries to a single snoop transaction and system therefor | Physics | 56 | Expired |
| US6499116B1 | Performance of data stream touch events | Physics | 42 | Expired |
| US6163835A | Method and apparatus for transferring data over a processor interface bus | Physics | 24 | Expired |
| US6785772B2 | Data prefetching apparatus in a data processing system and method therefor | Physics | 24 | Expired |
| US4193064A | Multiple pulse timer | Physics | 22 | Expired |
| US8615644B2 | Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition | Physics | 19 | Active |
| US6240479A | Method and apparatus for transferring data on a split bus in a data processing system | Physics | 18 | Expired |
| US6581140B1 | Method and apparatus for improving access time in set-associative cache systems | Physics | 17 | Expired |
| US8261047B2 | Qualification of conditional debug instructions based on address | Physics | 17 | Active |
| US5422914A | System and method for synchronizing data communications between two devices operating at different clock frequencies | Physics | 15 | Expired |
| US6321303A | Dynamically modifying queued transactions in a cache memory system | Physics | 12 | Expired |
| US8117618B2 | Forward progress mechanism for a multithreaded processor | Physics | 12 | Active |
| US7681021B2 | Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch | Physics | 11 | Active |
| US7852692B2 | Memory operation testing | Physics | 10 | Active |
| US9047079B2 | Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition | Physics | 10 | Active |
| US8156357B2 | Voltage-based memory size scaling in a data processing system | Emerging Cross-Sectional Technologies | 9 | Active |
| US7506105B2 | Prefetching using hashed program counter | Physics | 9 | Expired |
| US7849247B2 | Interrupt controller for accelerated interrupt handling in a data processing system and method thereof | Physics | 8 | Active |
| US7069384B2 | System and method for cache external writing and write shadowing | Physics | 7 | Expired |
| US8041901B2 | Performance monitoring device and method thereof | Physics | 6 | Active |
| US8539485B2 | Polling using reservation mechanism | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.