Method of fabricating dual cylindrical capacitor
US6074911A · kind A · utility
Inventors
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A method of fabricating a dual trench capacitor with a horn region is provided. On a semiconductor substrate having at least a device isolation structure and a transistor thereon, wherein the transistor includes at least a gate and a source/drain region, an insulation layer with an opening exposing the source/drain region is formed. The opening is partly filled with a conductive plug, the plug having a surface level lower than a surface level of the insulation layer, so that a trench with a side wall of the insulation layer is formed on the plug within the opening. A conductive spacer is formed on the side wall with a horn shape. A part of the insulation layer which encompassing the conductive plug and the conductive spacer is removed, so that a dual trench structure which exposes outer side walls of the conductive spacer and the conductive plug, and a part of the insulation layer is formed. A conformal conductive layer is formed to cover whole surfaces of the dual trench structure, the conductive spacer and the conductive plug, so that a bottom electrode formed by the conformal conductive layer, the conductive spacer and the conductive plug. A dielectric layer is formed on the bot…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.