Method for forming different area vias of dynamic random access memory
US6074912A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 8, 1999 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Feb 8, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming different area vias of dynamic random access memory is disclosed. Essential points of the invention comprise spacer is only formed on gate of periphery circuit, and depth of passivation layer of periphery circuit gates is larger than depth of layer that capped over gates of cell. The provided method comprises following steps: First, capping a layer over gate of cell and gate of periphery circuit and then forming spacer on gate of periphery circuit, where depth of capping layer is smaller than depth of passivation layer of periphery circuit gate. Second, both gate of cell and gate of periphery circuit are cover by a dielectric layer. Third, vias in both cell and periphery circuit are formed simultaneously by photolithography and etching, where etching comprises etching of dielectric layer and etching of passivation layer. Advantageous of the invention is only a photolithography process is necessary and then throughput is enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.