Semiconductor device having MIS transistors and capacitor
US6075266A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 9, 1998 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Jan 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
The capacitor dielectric film (35) and the poly silicon layer (36) are formed on the silicide film (32) of the upper electrode LE of the capacitor. Further, after the Ti and TiN layer (37) has been formed on the poly silicon layer (36) by spattering, the formed Ti and TiN layer (37) is allowed to react upon the poly silicon layer (36), to form the TiSi.sub.2 layer (38) of high melting point silicide film on the poly silicon layer (36). After that, before forming the barrier layer (40) and the wiring layer (42), the substrate (10) is cleaned as pre-processing by applying a voltage to the substrate (10). In this cleaning process, since the capacitor dielectric film (35) is protected by the TiSi.sub.2 layer (38) of high melting point silicide film, it is possible to prevent the capacitor dielectric film (35) from being damaged during the cleaning process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.