Apparatus and method for providing memory address interchanging for high speed memory accesses
US6075785A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Dec 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04Q2213/13393
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for accessing data of a telecommunications interface control RAM to meet the two different requirements of the two types of devices accessing the control RAM. Data for output ports are typically aligned such that time-slot 0 for each port leaves the network at the same time. The hardware therefore requests that the control RAM be organized such that the first N locations correspond to time-slot 0 of all output ports, the next N locations to time-slot 1 of all ports, and so on with the final N locations corresponding to the last time-slot of all ports. The software addressing under processor control, on the other hand, uses data structure groups which are a function of the communication ports. Connecting a least significant group of address lines address lines of a control bus respectively to a most significant group of address lines of the control RAM and connecting a more significant group of address lines of the control bus respectively to a least significant group of address lines of the control RAM provides linear addressing sequences of the control bus to result in every N th. control RAM location being accessed. Such addressing typically stores the firs…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.