Multiprocessor computer architecture incorporating a plurality of memory algorithm processors in the memory subsystem
US6076152A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Dec 17, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors ("MAP") in the memory subsystem. The MAP may comprise one or more field programmable gate arrays ("FPGAs") which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory ("ROM") located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time. A computer system memory structure MAP disclosed herein may function in normal or direct memory access ("DMA") modes of operation and, in the latter mode, one device may feed results directly to another thereby allowing pipelining or parallelizing execution of a user defined algorithm. The system of the present invention also provides a user programmable performance mo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.