Method and apparatus for testing a circuit module concurrently with a non-volatile memory operation in a multi-module data processing system
US6076177A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1997 |
| Grant date | Jun 13, 2000 |
| Priority date | — |
| Expiry date | Sep 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/2602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Testing of a multi-module data processing system (20) includes performing a functional test on a module (42, 44, 46, 48, 50, 54) concurrently with an erase operation of a non-volatile memory module (34, 36). Because the erase operation requires multiple clock cycles to complete, and little or no interaction with a tester, a set of test patterns may be run on one or more of the modules (42, 44, 46, 48, 50, 54) while the erase operation is being performed. Between each test pattern, a special reset signal is provided to a reset unit (39) of a system integration unit (38). The special reset signal resets the modules (42, 44, 46, 48, 50, 54), without affecting the erase operation of the flash memory module (34, 36), in order to perform each test of the modules (42, 44, 46, 48, 50, 54) from a known state. Concurrent testing in this manner reduces the time required to test a multi-module data processing system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.