Multi-chips semiconductor package and fabrication method
US6077724A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 5, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Sep 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multi-chips semiconductor package and fabrication method mainly combines LOC and BGA techniques to overlap one chip upon another chip in an IC component package. One chip uses leads of a lead frame as connection interface of the circuit in the chip to outside. Another chip uses solder balls as connection interface of the circuit in another chip to outside. The two chips are supported by the lead frame without a substrate used in a conventional BGA package. The two chips may have same or different function. The structure is simple and easy to produce at low cost. The size and length of the IC component is smaller than the one produced by conventional multi-chips packaging techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.