Method for forming a DRAM having improved capacitor dielectric layers
US6077737A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Jun 2, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a DRAM device having nitride/oxide or tantalum pentoxide dielectric layers. The method includes: forming field oxide regions on a substrate to define active regions; forming at each active region a MOSFET comprising a top dielectric layer; forming a contact window in the MOSFET top dielectric layer; generating a doped poly-Si bottom electrode of a capacitor in electrical connection with the MOSFET through the contact window; removing surface oxide of the bottom electrode using both chemical and inductive coupled plasma (ICP) treatments; depositing nitride/oxide dielectric layers or a tantalum pentoxide dielectric layer on the ICP-treated bottom electrode; generating a doped poly-Si top electrode of the capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.