Semiconductor device having mutually different two gate threshold voltages
US6078067A · kind A · utility
15Cited by
3References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 29, 1997 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Sep 29, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0135
Abstract
On a semiconductor substrate, a channel layer, an electron supply layer, a third semiconductor layer, a second etching stopper layer, a second semiconductor layer and a first etching stopper layer and a first semiconductor layer are grown in sequential order to form E-type and D-type FETs. The third semiconductor layer and the second semiconductor layer have equal layer thickness, and the second etching stopper layer and the first etching stopper layer have the equal layer thickness. Thus, Vth of the E-type and D-type FETs can be controlled at the predetermined value with high reproduction ability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.