Accelerated graphics port programmable memory access arbiter
US6078338A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Mar 11, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/363
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.