Method and structure for controlling operation of a DRAM array
US6078547A · kind A · utility
7Cited by
4References
10Claims
0Family size
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Key dates
| Filing date | May 12, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | May 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each system clock signal period into three parts, thus providing four control signals fixed phase relationship per clock period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.