Multiprocessor system having distinct data bus and address bus arbiters
US6078983A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 1997 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | May 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1605
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.