Dirty line cache
US6078992A · kind A · utility
46Cited by
17References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 5, 1997 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Dec 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for providing a dirty line cache to supplement a cache memory, in order to improve caching performance for a processor in a computer system. A fully-associative cache memory is coupled to operate with a main cache memory at a particular level of the cache hierarchy. The supplemental cache is termed as a dirty line cache, since it only stores dirty cache lines. In the preferred embodiment, the dirty line cache is implemented in a write-out buffer of a write-back or write-through cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.