Herbert Hum
74Patents
12h-index
106Co-inventors
87Inventor score
Filing activity: Dec 5, 1997 → Jul 5, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6078992A | Dirty line cache | Physics | 46 | Expired |
| US6922756B2 | Forward state for use in cache coherency in a multiprocessor system | Physics | 32 | Expired |
| US6798364B2 | Method and apparatus for variable length coding | Electricity | 29 | Expired |
| US8615647B2 | Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state | Emerging Cross-Sectional Technologies | 25 | Active |
| US7257693B2 | Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said system | Physics | 20 | Expired |
| US6922745B2 | Method and apparatus for handling locks | Physics | 19 | Expired |
| US6594730B1 | Prefetch system for memory controller | Physics | 19 | Expired |
| US6954829B2 | Non-speculative distributed conflict resolution for a cache coherency protocol | Physics | 17 | Expired |
| US7360033B2 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system | Physics | 16 | Active |
| US6675282B2 | System and method for employing a global bit for page sharing in a linear-addressed cache | Physics | 16 | Expired |
| US7095342B1 | Compressing microcode | Electricity | 15 | Expired |
| US6643743B1 | Stream-down prefetching cache | Physics | 15 | Expired |
| US7269698B2 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system | Physics | 12 | Expired |
| US7512750B2 | Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of information | Physics | 12 | Expired |
| US9626321B2 | High performance interconnect | Emerging Cross-Sectional Technologies | 12 | Active |
| US7434006B2 | Non-speculative distributed conflict resolution for a cache coherency protocol | Physics | 12 | Active |
| US7996572B2 | Multi-node chipset lock flow with peer-to-peer non-posted I/O requests | Physics | 11 | Active |
| US9829965B2 | Distribution of tasks among asymmetric processing elements | Emerging Cross-Sectional Technologies | 10 | Active |
| US8392665B2 | Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines | Physics | 9 | Active |
| US7080209B2 | Method and apparatus for processing a load-lock instruction using a relaxed lock protocol | Physics | 8 | Expired |
| US7111128B2 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system | Physics | 8 | Expired |
| US7130969B2 | Hierarchical directories for cache coherency in a multiprocessor system | Physics | 8 | Expired |
| US8789031B2 | Software constructed strands for execution on a multi-core architecture | Physics | 8 | Active |
| US7958336B2 | System and method for reservation station load dependency matrix | Physics | 8 | Active |
| US6954822B2 | Techniques to map cache data to memory arrays | Physics | 8 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.