Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state
US6079014A · kind A · utility
59Cited by
13References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 2, 1997 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Sep 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is disclosed comprising a front end circuit that fetches a series of instructions according to a program sequence determined by at least one branch prediction, a register renaming circuit that allocates execution resources to each instruction, and an execution circuit that executes each instruction in the instruction stream. The execution circuit causes the front end circuit to refetch the series of instructions if a branch misprediction is detected. A stall signal disables the register renaming circuit until the execution circuit commits the branch result to an architectural state according to the program sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.