Method for generating a Shmoo plot contour for integrated circuit tester
US6079038A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 1998 |
| Grant date | Jun 20, 2000 |
| Priority date | — |
| Expiry date | Apr 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31937
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of operating an integrated circuit (IC) tester is disclosed in which an IC is repeatedly tested with respect to a limited number of combinations of values of two variable IC operating parameters (X and Y) to determine the boundary of a two-dimensional range of combinations of values of the X and Y parameters for which the IC passes a test. After finding a combination of X and Y parameter values on the boundary, each combination of parameter values to be tested thereafter is selected by altering either the X or Y parameter value, with the decision based on whether the IC passed the last test and on the manner in which a last tested combination of X and Y parameter values was selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.