Dual damascene
US6080663A · kind A · utility
28Cited by
4References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1998 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Nov 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7681
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A dual damascene process is provided. A dielectric layer is formed on a substrate having a conductive region. The dielectric layer is selectively doped to form a doped region aligned over the conductive region. The doped region, the dielectric layer underlying the doped region, and another part of the undoped dielectric layer are etched until the conductive region is exposed, so that a dual damascene opening exposing the conductive region and a trench are formed, wherein the dual damascene opening comprising a upper trench and a lower via hole. The dual damascene opening and the trench are filled with a conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.