Semiconductor chip package structure
US6081038A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1999 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Apr 5, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The object of the present invention is to provide a semiconductor chip package structure in which thermal stress exerted on a wiring substrate is mitigated to improve the reliability of the bond between the semiconductor chip and the wiring substrate and the bond between the wiring substrate and the motherboard. To achieve the above object, the present invention provides a semiconductor chip package structure in which a semiconductor chip is mounted on a wiring substrate by flip chip bonding to a wiring pattern on the wiring substrate, comprising: a large number of electrode terminals disposed on an electrode arrangement surface of the semiconductor chip; a first group of the electrode terminals electrically connected to the wiring pattern by an adhesive layer; and a second group of the electrode terminals electrically connected to the wiring pattern by an elastomer layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.