Bit line control circuit for a memory array using 2-bit non-volatile memory cells
US6081456A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 4, 1999 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Feb 4, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bit line control circuit for accessing an array of 2-bit non-volatile memory cells. Each memory cell has a first and a second charge trapping regions. A set of bit lines extends between the array and the bit line control circuit. The bit line control circuit includes pass transistors that selectively route pairs of bit lines to corresponding voltage control circuits in either a first order or a second (reversed) order. This enables both the first and second charge trapping regions of the memory cells to be accessed from the same voltage control circuits. In one embodiment, the bit line control circuit includes a first-level pass transistor coupled to each bit line. A second set of bit lines is coupled to the first-level pass transistors. A parallel-connected pair of second-level pass transistors is coupled to each bit line in the second set of bit lines. A third set of bit lines is coupled to the second-level pass transistors. The voltage control circuits are coupled to the third set of bit lines. The voltage control circuits apply voltages to the third set of bit lines to perform read, write and erase operations in the memory cells of the memory array. The first and second level…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.