Hierarchical prefetch for semiconductor memories
US6081479A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Jun 15, 1999 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Jun 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory in accordance with the present invention includes a data path including a plurality of hierarchical stages, each stage including a bit data rate which is different from the other stages. At least two prefetch circuits are disposed between the stages. The at least two prefetch circuits include at least two latches for receiving data bits and storing the data bits until a next stage in the hierarchy is capable of receiving the data bits. The at least two prefetch circuits are coupled between stages such that an overall data rate per stage between stages are substantially equal. Control signals control the at least two latches such that prefetch circuits maintain the overall data rate between the stages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.