Patent · US Expired

Cache reloading performance improvement through the use of early select techniques with and without pipelining

US6081872A · kind A · utility

15Cited by

5References

28Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Richard E. Matick · Cortland, US
Stanley E. Schuster · Granite Springs, US

Key dates

Filing date	Jul 7, 1997
Grant date	Jun 27, 2000
Priority date	—
Expiry date	Jul 7, 2017

Classification

Technology area (CPC G)Physics
CPC primaryG06F12/0897
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A DRAM for L2 cache is used in a computer memory hierarchy without compromising overall system performance. By proper organization and design, the DRAM L2 cache is many times larger than a SRAM implementation in the same technology, but without compromising overall system performance. The larger DRAM capacity compared to a SRAM gives a substantially better HIT ratio which compensates for any small degradation due to access time. To achieve this, it is essential to minimize the total DRAM access time as much as possible by the use of early select techniques and pipelining.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.