Circuit for allowing a two-pass fuse blow to memory chips combining an array built-in self-test with redundancy capabilities
US6081910A · kind A · utility
20Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1994 |
| Grant date | Jun 27, 2000 |
| Priority date | — |
| Expiry date | Apr 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit that enhances the testability of an integrated circuit of a memory type and which identifies defective redundant word lines in a state of the art SRAM macro that combines an ABIST structure with a redundancy mechanism. The circuit allows a two-pass fuse blow after completing the burn-in process that significantly increases the manufacturing yield and repairability of the SRAM macro.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.