Digital integrated circuit design system and methodology with hardware
US6083269A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1997 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Aug 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of designing an integrated circuit employs hardware testing rule checking so as to ensure hardware testability and to ensure that automated test program generation will succeed when the design cycle reaches that stage. The method calls for, first, receiving a proposed logic design defined at a functional or behavioral level; second, defining a test bench for simulating operation of the logic design, the test bench including at least one input vector for stimulating the logic design for verifying the operation of the logic design; receiving a predetermined set of one or more hardware testing rules associated with a target tester; simulating operation of the logic design using the test bench; and, prior to releasing the logic design for logic synthesis, checking the simulation for compliance with the hardware testing rule set. Preliminary checking of the design and test bench prior to synthesis can avoid costly corrections later in connection with test program generation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.