Method for producing semiconductor memory device having a capacitor
US6083765A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 18, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Aug 18, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
A semiconductor memory device includes a semiconductor substrate having a surface defining a plane extending substantially parallel thereto. A multiplicity of memory cells disposed on the substrate each have a selection transistor disposed in the plane. The transistor has a gate terminal and first and second electrode terminals. Each of the memory cells has a storage capacitor associated with and triggerable by the transistor. The capacitor has a ferroelectric dielectric and first and second capacitor electrodes. The capacitor has a configuration projecting upward from the plane and is disposed inside a trench extending as far as the second electrode terminal of the transistor. A word line is connected to the gate terminal of the transistor, a bit line is connect to the first electrode terminal of the transistor, and a common conductor layer of electrically conductive material is connected to the first capacitor electrode of the capacitor. A method for producing the device includes producing the capacitor after production of the transistor and metallizing layers associated with the transistor for connection of the word and bit lines, in a configuration projecting upward from the pl…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.