Power MOSFET device having low on-resistance and method
US6084268A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 1997 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Nov 3, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41) of the device. The one or more localized regions of doping (61,62,63) are spaced apart from the body regions (44,46) to avoid detrimentally impacting device breakdown voltage. In an alternative embodiment, a groove (122) or trench (152) design is incorporated to reduce JFET resistance (34). In a further embodiment, a gate dielectric layer having a thick portion (77,97,128,158) and thin portions (76,126,156) is incorporated to enhance switching characteristics and/or breakdown voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.