PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays
US6084429A · kind A · utility
272Cited by
11References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 24, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Apr 24, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks, interconnect, and routing wires may be accomplished with switch matrices and programmable interconnect points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.