Circuits and methods for burn-in of integrated circuits using potential differences between adjacent main word lines
US6084808A · kind A · utility
2Cited by
12References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Nov 25, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
External address signals are applied to an integrated circuit in a burn-in test mode. The external address signals control the voltage levels of adjacent main word lines in a memory array in the integrated circuit. The adjacent main word lines may thereby be configured in to be in opposing logic states. The opposing logic states may provide a potential difference between the adjacent main word lines, thereby increasing the likelihood of detecting microbridges between the adjacent main word lines formed during fabrication of the integrated circuit. The reliability of the integrated circuit may thereby be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.