Apparatus and method for providing non-blocking pipelined cache
US6085292A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 1997 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Jun 5, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that the address cache is probed. A memory controller receives the missed addresses from the address queue. A data queue receives data stored at the missed addresses from the memory controller. A probe result queue is connected to the address cache for storing data cache line addresses and hit/miss information. A multiplexer connected to the data cache, the data queue, and the probe result queue selects output data from the data cache or the data queue depending on the hit/miss information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.