Computer processor system for executing RXE format floating point instructions
US6085313A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Apr 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer processor system having a floating point processor for instructions which are processed in a six cycle pipeline, in which prior to the first cycle of the pipeline an instruction text is fetched, and during the first cycle for the fetched particular instruction it is decoded and the base (B) and index (X) register values are read for use in address generation. Instructions of the RX-type are extended by placing the extension of the operation code beyond the first four bytes of the instruction format and to assign the operation codes in such a way that the machine may determine from the first 8 bits of the operation code alone, the exact format of the instruction. Instructions formats include the ESA/390 instructions SS, RR; RX; S; RRE; RI: and the new RXE instructions. where instructions of the RXE format have their R.sub.1, X.sub.2, B.sub.2, and D.sub.2 fields in the identical positions in said instruction register as in the RX format to enable the processor to determine from the first 8 bits of the operation code alone that an instruction being decoded is an RXE format instruction and the register indexed extensions of the RXE format instruction, after which it gates th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.