Control circuit for switching a processor between multiple low power states to allow cache snoops
US6085330A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1998 |
| Grant date | Jul 4, 2000 |
| Priority date | — |
| Expiry date | Apr 7, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power consumption is conserved in a computer system by, instead of forcing a processor to change from the stop clock state to a fully operational state, allowing the processor to transition from the stop clock state to the stop grant state. The stop grant state allows snoops so that the processor handles subsequent bus cycles and snoops that take place during the bus cycles. Following the snoops, the processor transitions back from the stop grant state to the stop clock state. In one embodiment, an automatic control circuit is connected to a processor in a computer system. When the processor is in the stop clock state, the automatic control circuit responds to a bus request, not by transitioning to the fully operational state, but instead by transitioning from the stop clock state to the snoopable stop grant state in which the processor clock is operating. The automatic control circuit allows the snoop to take place then, when the snoop is complete, automatically transitions the processor back to the stop clock state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.